[1]
FNU Parshant, “ADVANCING HPC ARCHITECTURE: INTEGRATION OF SCALABLE INTERCONNECTS WITH ENERGY-EFFICIENT SYSTEM-ON-CHIP DESIGNS”, IJCET, vol. 16, no. 01, pp. 1300–1313, Jan. 2025, Accessed: Mar. 24, 2026. [Online]. Available: https://ijcet.in/index.php/ijcet/article/view/282