RECONFIGURABLE FPGA-BASED ACCELERATION OF RTL SIMULATION AND CO-SIMULATION FOR DATACENTER WORKLOADS

Abstract

The increasing complexity and scale of System-on-Chip (SoC) designs, particularly those tailored for datacenter applications such as NVMe storage and RDMA networking, have placed significant demands on functional verification methodologies. Traditional RTL simulation struggles to meet performance requirements for large-scale testbenches, particularly in pre-silicon validation stages. This work proposes a reconfigurable FPGA-based architecture that accelerates RTL simulation and co-simulation workflows using dynamic partial reconfiguration (DPR). By partitioning the verification workload and leveraging runtime FPGA reconfiguration, the proposed framework achieves significant speedups in simulation cycles, reduces verification turnaround time, and facilitates continuous integration for cloud-scale SoC workloads. Our design integrates FPGA emulation with software simulation, enabling rapid prototyping and system validation in hybrid hardware/software environments. Experimental evaluations demonstrate performance gains of 10x–50x over traditional simulators in representative datacenter scenarios. These findings suggest that reconfigurable FPGA platforms can dramatically improve verification efficiency for storage and networking SoCs.